"Energy-Efficient Edge-Native Sensory Processing"
The Neuromorphic Computer Architecture Lab (NCAL) is a new research group in the Electrical and Computer Engineering Department at Carnegie Mellon University, and is under the leadership of Prof. John Paul Shen and Prof. James E. Smith, along with industry adviser Quinn A. Jacobson.
RESEARCH GOAL: A processor architecture that captures the capabilities and efficiencies of brain's neocortex for energy-efficient edge-native real-time sensory processing in mobile and edge devices.
Capabilities: strong adherence to biological plausibility and spike timing dependent plasticity (STDP) in order to enable continuous, unsupervised, emergent learning.
Efficiencies: can achieve several orders of magnitude improvement on energy efficiency as compared to existing ANN/DNN computation infrastructure for supporting AI/ML/DL workloads.
Targeted Applications: Edge-Native Sensory Processing
Computational Model: Space-Time Algebra (STA)
Processor Architecture: Temporal Neural Networks (TNN)
Processor Design Style: Generalized Race Logic (GRL)
Hardware Implementation: Off-the-Shelf Digital CMOS
1. Targeted Applications: Edge-Native Sensory Processing
Targeted application domain: real-time edge-native sensory processing that mimics the human visual cortex. The end result of this research will be temporal neural networks that can achieve brain-like capabilities with brain-like efficiencies and be implemented with standard CMOS technology. This effort can enable a whole new family of accelerators, or sensory processing units, that can be deployed in mobile and edge devices for performing real-time, edge-native, always-on, sensory processing and inference, while consuming only a few milliwatts.
2. Computational Model: Space-Time Algebra (STA)
A new Space-Time Computing (STC) Model has been developed for computing that communicates and processes information encoded as transient events in time -- action potentials or voltage spikes in the case of neurons. Consequently, the flow of time becomes a freely available, no-cost computational resource. The theoretical basis for the STC model is the "Space-Time Algebra“ (STA) with primitive elements that model points in time and functional operations that are consistent with the flow of Newtonian time. [STC/STA was developed by Jim Smith]
3. Processor Architecture: Temporal Neural Networks (TNN)
Temporal Neural Networks (TNNs) are a special class of spiking neural networks, based on the space time algebra, and shown to be capable of implementing any space time function. By exploiting time as a computing resource, TNNs are capable of performing sensory processing with very low system complexity and very high energy efficiency, as compared to current ANNs and DNNs. Furthermore, the key feature of TNNs is the capability for learning that is unsupervised, continuous, and emergent.
4. Processor Design Style: Generalized Race Logic (GRL)
Standard CMOS Implementation of TNNs can be achieved using voltage level transitions (edges) rather than voltage spikes. CMOS logic gates can be re-purposed to implement temporal operators in a highly energy-efficient way using the recently proposed "Generalized Race Logic" (GRL) approach. Using space-time algebra as the basis, and the GRL design method and tools, useful and special purpose TNN-based sensory processing units can be implemented using current CMOS design tools and fabrication technology. [GRL was first proposed by Tim Sherwood et al. at UCSB and then enhanced by Jim Smith]
5. Hardware Implementation: Off-the-Shelf Digital CMOS
Based on the STC/STA theoretical foundation and the GRL design style using standard CMOS, we can design special purpose "Sensory Processing Units" (SPU) for various edge-native real-time sensory processing needs. A new library of GRL-based macro blocks can be created and used by designers to then create useful SPUs, which can become reusable IP blocks for integration in SoCs. One challenge is to ensure that these SPUs are compatible and can easily interface with an existing/enhanced API for purpose-specific accelerators.